Eclipse 512 Dokumentacja Pobierz pdf (Strona 82)

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82 GL-S MirrorBit

Family IS29GL_128S_01GS_00_Rev.A February 2015

Data Sheet

Figure 10.5 Back to Back Read (t

ACC

) Operation Timing Diagram

Figure 10.6 Back to Back Read Operation (t

)Timing Diagram

Note:

Back to Back operations, in which CE# remains Low between accesses, requires an address change to initiate the second access.

Figure 10.7 Page Read Timing Diagram

Note:

Word Configuration: Toggle A0, A1, A2, and A3.

Amax-A0

CE#

OE#

DQ15-DQ0

tACC

tOE

tCE

tDF

tOH

Amax-A0

CE#

OE#

DQ15-DQ0

tRC

tACC

tOE

tCE

tDF tOH

tOH

Amax-A4

A3-A0

CE#

OE#

DQ15-DQ0

tACC

tOE

tCE

tPACC

1 2 ... 77 78 79 80 81 82 83 84 85 86 87 ... 99 100

GL-S MirrorBit 1
Eclipse 1
Non-Volatile Memory Family 1
2 GL-S MirrorBit 2
Performance Summary 4
Table of Contents 5
6 GL-S MirrorBit 6
Family 7 7
8 GL-S MirrorBit 8
1. Product Overview 10
Family 11 11
Software Interface 12
2.1 Flash Memory Array 13
14 GL-S MirrorBit 14
2.3 Status Register ASO 15
2.4 Data Polling Status ASO 16
2.5 Secure Silicon Region ASO 16
2.6 Sector Protection Control 17
3.1 Device Protection Methods 18
3.2 Command Protection 18
3.4 Sector Protection Methods 19
3.4.3 PPB Lock 20
3.4.7 Lock Register 21
22 GL-S MirrorBit 22
Family 23 23
4.1 Asynchronous Read 24
4.2 Page Mode Read 24
5. Embedded Operations 25
5.2 Program and Erase Summary 26
5.3 Command Set 27
28 GL-S MirrorBit 28
Family 31 31
5.3.3 Blank Check 32
5.3.4 Erase Methods 32
5.3.4.2 Sector Erase 33
34 GL-S MirrorBit 34
5.3.6 ASO Entry and Exit 35
5.3.6.4 Lock Register ASO 36
5.3.6.5 Password ASO 36
5.3.6.6 PPB ASO 36
5.3.6.7 PPB Lock ASO 36
5.4 Status Monitoring 37
5.4.2 Data Polling Status 38
5.4.2.1 DQ7: Data# Polling 39
5.4.2.2 DQ6: Toggle Bit I 40
5.4.2.4 DQ2: Toggle Bit II 40
Family 41 41
42 GL-S MirrorBit 42
Family 43 43
5.5.2 Protection Error 44
5.5.3 Write Buffer Abort 45
6.1 Command Summary 57
60 GL-S MirrorBit 60
Hardware Interface 65
7.2 Input/Output Summary 65
7.3 Versatile I/O Feature 65
7.4 Ready/Busy# (RY/BY#) 66
7.5 Hardware Reset 66
8.1 Interface States 67
8.3 Power Conservation Modes 68
8.4 Read 68
8.5 Write 69
8.5.3 Logical Inhibit 70
9.1 Absolute Maximum Ratings 71
9.2 Latchup Characteristics 71
9.3 Operating Ranges 71
Figure 9.1 Power-up 72
9.3.4 Input Signal Overshoot 73
9.4 DC Characteristics 74
10.2 AC Test Conditions 77
78 GL-S MirrorBit 78
10.3.2 Hardware (Warm) Reset 79
10.4 AC Characteristics 80
Family 81 81
82 GL-S MirrorBit 82
Table 10.7 Write Operations 83
) Operation Timing Diagram 84
11.1 56-Pin TSOP 91
11.1.2 Physical Diagram 92
11.2 64-Ball FBGA 93
11.3 56-Ball FBGA 96
13. Ordering Information 98
Data Sheet 100

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